Semiconductor device including a planarized surface and method thereof

ABSTRACT

A method of planarizing the surface of a semiconductor substrate to reduce the occurrence of a dishing phenomenon. A patterned etch stop layer defining a trench region is formed on a substrate. The substrate is etched to form a trench region, and a medium material layer and an oxide layer are subsequently formed on the substrate, filling the trench region. Chemical mechanical polishing (CMP) is performed on the oxide layer until the medium material layer is exposed. CMP is then performed until the patterned etch stop layer is exposed and a planarized oxide layer is formed. Because the medium material layer has a higher removal rate during CMP than the oxide layer, occurrences of the dishing phenomenon are reduced. A slurry including an anionic surfactant is used to increase the CMP removal ratio of the medium material layer to the oxide layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional application claims priority under 35 U.S.C.§119 to Korean Patent Application No. 2002-46575, filed Aug. 7, 2002 inthe Korean Intellectual Property Office, the contents of which areincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of semiconductordevices, and more particularly, to a method of planarizing the surfaceof a semiconductor device and reduce the occurrence of the dishingphenomenon and a semiconductor device manufactured according to themethod. The present invention also relates to a method of increasing theremoval rate ratio of a medium material layer to an oxide layer duringchemical mechanical polishing (CMP).

2. Description of the Related Art

As the density and size of semiconductor devices decrease and theinterconnection structure of semiconductor devices are multiplied, theheight of the steps on the surfaces of the semiconductor devices haveincreased. In order to planarize the surface steps, a spin-on glass(SOG) process, an etch back process, or a chemical mechanical polishing(CMP) process is typically used.

When CMP is used as a wide area planarizing technique, a wafer surfaceis pressed against a polishing pad while an abrasive slurry flows to acontact area of the wafer and the polishing pad. The wafer surfacechemically reacts with the slurry, while the polishing pad and thewafer, which rotate relative to each other, physically planarizeirregularities on the wafer surface.

FIGS. 1 and 2 are cross-sectional views illustrating a conventionalmethod of separating an active region, where operations of asemiconductor device occur, from a field region, which is an inactiveregion, by filling a trench with an oxide layer in a shallow trenchisolation (STI) process and planarizing the surface of the oxide layerusing CMP.

Referring to FIG. 1, an etch stop layer 12 for CMP (e.g., a siliconnitride layer) is formed on a silicon substrate 10. A photolithographyprocess using a photoresist layer (not shown) is then performed so thatan etch stop layer pattern is formed which defines a region wheretrenches will be located. Next, the silicon substrate 10 is etched usingthe etch stop layer pattern as an etch mask so that a trench region 14having a desired depth is formed. A silicon oxide layer 16 isblanket-deposited on the silicon substrate 10 and the trench region 14.As a result, the trench region 14 is filled with an oxide layer havingan excellent gap-fill characteristic.

Optionally, a pad oxide layer (not shown) may be formed on the substrate10 before the etch stop layer 12 (e.g., silicon nitride layer) isformed. In another example, a thermal oxide layer (not shown) or a linerlayer (not shown) may be formed on the bottom and the sidewalls of thetrench region 14 before the silicon oxide layer 16 is deposited in thetrench region 14.

Referring to FIG. 2, CMP is performed on the silicon oxide layer 16 toexpose the etch stop layer 12. Thereafter, the etch stop layer 12 isremoved so that a field region for isolating devices is formed. In thefield region, the trench region 14 in the silicon substrate 10 is filledwith a silicon oxide layer 16 a.

A plurality of trench regions 14 having various widths can be formed inthe silicon substrate 10 depending upon the circuit design. When thewidth of the trench region 14 is large, a large amount of the siliconoxide layer 16 remains after CMP. As a result, CMP is excessivelyperformed to remove the remaining silicon oxide layer 16. Thus, a largeamount of the silicon oxide layer 16 in the trench region 14 (which hasa relatively small width) is removed, which results in a dishingphenomenon (e.g., the silicon oxide layer 16 has a concave shape), as isshown in FIG. 2. Because the dishing phenomenon deteriorates the surfaceplanarity of the silicon substrate and causes defects in thesemiconductor device, it is desirable to reduce the occurrence of thedishing phenomenon.

SUMMARY OF THE INVENTION

At least one exemplary embodiment of the present invention provides amethod of planarizing the surface of a semiconductor device to reducethe occurrence of a dishing phenomenon. A patterned etch stop layer,such as a patterned silicon nitride layer, which defines a trenchregion, is formed on a base material layer (e.g., a substrate). Thesubstrate is etched to form a trench region, and a medium material layerand a buried material layer (e.g., an oxide layer) are subsequentlyformed on the substrate to fill the trench region. The medium materiallayer can be formed over the entire surface of the substrate, e.g., onthe patterned etch stop layer and in the trench region, or it can beformed on the patterned etch stop layer and not in the trench region.Alternatively, the medium material layer can be selectively removed fromthe trench layer. Any material that has a higher removal rate duringchemical mechanical polishing (CMP) is suitable for use as the mediummaterial layer. A boron phosphorous silicate glass (BPSG) may be used asthe medium material layer and a PE-TEOS oxide layer, a USG oxide layer,or an HDP oxide layer may be used as the oxide layer.

Once the medium material layer and the oxide layer are formed on thesubstrate and the trench region is filled, a first CMP process isperformed on the oxide layer until the medium material layer is exposed.A second CMP process is then performed until the patterned etch stoplayer is exposed and a highly planarized oxide layer is formed. Becausethe medium material layer has a higher removal rate in the CMP processesthan the oxide layer, occurrences of the dishing phenomenon can bereduced.

In addition, a slurry that includes an anionic surfactant can be used toincrease the CMP removal ratio of the medium material layer to the oxidelayer. Exemplary embodiments use a ceria-based abrasive that includesammonium polycarboxylate (APC) as an additive. The APC can be added tothe slurry in an amount of approximately 2.0 to 4.5 parts by weight. Theadsorption of APC onto the oxide layer decreases the removal rate of theoxide layer. Further, the polishing rate ratio of the medium materiallayer (e.g., BPSG layer) to the oxide layer may be at least 10:1 duringCMP.

Additionally, at least one exemplary embodiment of the present inventionprovides a semiconductor device that includes a base material layer,such as a silicon substrate, that includes a depression region (e.g., atrench region), a medium material layer formed on the bottom of thedepression region, and a buried material layer positioned on the mediummaterial layer. The medium material layer and the buried material layerfill the depression region. In addition, the buried material layer has aplanarized surface.

The base material layer may be an insulating material layer or aconductive material layer formed on a silicon substrate. Any materialthat has a higher polishing removal rate than the buried oxide layer canbe used. In at least one exemplary embodiment, the etch stop layer is asilicon nitride layer, and the buried material layer is an oxide layer,such as, for example, a PE-TEOS layer, an HDP oxide layer, or a USGlayer. The medium material layer may be a BPSG layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will be readilyunderstood with reference to the following detailed description thereofprovided in conjunction with the attached drawings in which:

FIGS. 1 and 2 are cross-sectional views illustrating a conventionalmethod for planarizing the surface of a semiconductor device;

FIGS. 3 through 6 are cross-sectional views illustrating a method forplanarizing the surface of a semiconductor according to an exemplaryembodiment of the present invention; and

FIG. 7 is a graph illustrating the removal rate and the removal rateratio of a medium material layer and a buried material layer accordingto the density of an additive added to a slurry when performing a methodfor planarizing the surface of a semiconductor according to at least oneexemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will now be describedmore fully with reference to the accompanying drawings, in whichexemplary embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas being limited to the exemplary embodiments set forth herein. Rather,these exemplary embodiments are provided so that this disclosure can bethorough and complete and will fully convey the concept of the presentinvention to those skilled in the art. In the drawings, the thickness oflayers and regions are exaggerated for clarity. It will also beunderstood that when a layer is referred to as being “on” another layeror substrate, it can be directly on the other layer or substrate, orintervening layers may also be present. The same reference numerals indifferent drawings represent the same elements. Similarly, throughoutthe specification, like numbers refer to like elements.

FIGS. 3 through 6 are cross-sectional views illustrating a methodaccording to at least one exemplary embodiment of the present inventionfor separating a semiconductor device into an active region, whereoperations of the semiconductor device occur, and a field region, whichis an inactive region, by filling trenches with an oxide layer in ashallow trench isolation (STI) process and planarizing the surface ofthe semiconductor device using a planarizing process (e.g., a chemicalmechanical polishing (CMP) process).

Referring to FIG. 3, an etch stop layer (not shown), for example, asilicon nitride layer, for CMP is formed on a base material layer (e.g.,a silicon substrate 20) as a target layer for a surface planarizingprocess. Thereafter, a photolithography process using a photoresistlayer (not shown) is performed so that a silicon nitride layer pattern22 defining a trench region 24 is formed. Optionally, a pad oxide layer(not shown) may be deposited on the silicon substrate 20 before the etchstop layer (e.g., silicon nitride layer) is deposited in order to form adual-layered etch stop layer that includes the silicon nitride layer andthe pad oxide layer.

The silicon substrate 20 is etched using the silicon nitride layerpattern 22 as an etch mask to form a trench region 24 having a desireddepth. A medium material layer (e.g., a boron phosphorus silicate glass(BPSG) layer 27), is then blanket-deposited over the silicon substrate20 and the trench region 24. Alternatively, the BPSG layer 27 can beformed on the silicon nitride layer and not in the trench region 24 orthe BPSG layer 27 can be selectively removed from the trench region 24so that the BPSG layer is formed on the silicon nitride layer and not inthe trench region 24.

The BPSG layer 27 may be used as the medium material layer because theBPSG layer 27 is weak due to the presence of boron and phosphorus. As aresult, the BPSG layer 27 has a higher removal rate during CMP than aburied material layer (e.g., an oxide layer) which, as described below,fills the trench region 24 in a subsequent process. Although BPSG isspecifically disclosed herein as an example of the medium material, anymaterial having a higher removal rate during CMP than the buriedmaterial layer can be used as the medium material layer. When adifference between the polishing removal rate of the buried materiallayer and the polishing removal rate of the medium material layerexists, occurrences of the dishing phenomenon can be reduced.

Referring to FIG. 4, a buried oxide layer 28 is blanket-deposited on theBPSG layer 27 to fill the trench region 24. As a result, the trenchregion 24 is filled with an oxide layer having excellent gap-fillcharacteristics. Suitable examples of the oxide layer include, but arenot limited to, a PE-TEOS oxide layer, a USG oxide layer, and an HDPoxide layer. Optionally, a thermal oxide layer (not shown) or a siliconliner layer (not shown) can be formed on the bottom and the sidewalls ofthe trench region 24 before the buried oxide layer 28 is deposited inthe trench region 24.

Referring to FIG. 5, a first CMP is performed on the buried oxide layer28 on the surface of the silicon substrate 20 until the surface of theBPSG layer 27 is exposed. A concave buried oxide layer 28 a may beformed in the trench region 24 depending upon the width of the trenchregion 24.

Referring to FIG. 6, a second CMP is performed until the surface of thesilicon nitride layer 22 is exposed. This second CMP forms a highlyplanarized buried oxide layer 28 b, which reduces the occurrence of thedishing phenomenon. Optionally, the silicon nitride layer 22 can beremoved to form a trench device isolation region.

As discussed above, during CMP, a wafer surface is pressed against apolishing pad while an abrasive slurry flows to a contact area of thewafer and the polishing pad. In exemplary embodiments of the presentinvention, a slurry is used to increase the difference between thepolishing removal rate of the buried oxide layer 28 and the polishingremoval rate of the BPSG layer 27. In general, the CMP removal rate ofthe BPSG layer is higher than that of the oxide layer, which, asdescribed above, may be a PE-TEOS oxide layer, a USG oxide layer, or anHDP oxide layer. The CMP removal rates of the layers change depending onthe reflow condition of the BPSG layer 27, the densities of boron andphosphorous in the BPSG layer 27, and the type of slurry used.

An experiment was performed to determine how the CMP removal rate andthe removal rate ratio, e.g., selectivity, of a PE-TEOS oxide layer anda BPSG layer change according to the type of slurry used. In theexperiment conducted, an AMAT Mirra polisher was used, and IC1000 andSuba4 were used as a top pad and a sub pad of a platen pad,respectively. Slurry-A is a silica-based slurry and slurry-B1 andslurry-B2 are ceria-based slurries. The results of the experiment areshown in Table 1.

TABLE 1 PE-TEOS Removal rate Slurry removal rate BPSG removal rate ratioslurry-A 2,226 Å/min 6,122 Å/min 2.7 slurry-B1 2,260 Å/min 5,200 Å/min2.3 slurry-B2 4,985 Å/min 8,346 Å/min 1.7

Referring to Table 1, although the molecular structure of the BPSG layerand the molecular structure of the oxide layer are similar, themolecular structure of the BPSG layer is weak due to the inclusion ofboron and phosphorus. As a result, the CMP removal rate of the BPSGlayer is typically higher than the CMP removal rate of the oxide layer.For example, the removal rate ratio of the BPSG layer to the oxide layercan be one to three.

A second experiment was performed to determine if the CMP removal rateratio of the BPSG layer to the oxide layer could be increased. In thesecond experiment, an AMAT Mirra polisher was used, and IC1000 and Suba4were used as the top pad and the sub pad of the platen pad,respectively. The slurry was a silica-based slurry that included anabrasive in an amount of 1 part by weight. The amount of additive addedto the slurry was varied and the removal rate was measured. The additiveadded to the slurry was an anionic surfactant, such as ammoniumpolycarboxylate (APC)

It was determined that the difference between the polishing removal rateof the BPSG layer and the polishing removal rate of the PE-TEOS layerincreases depending on the amount of APC added to the slurry. Theresults of the experiment are illustrated in Table 2 and in FIG. 7.

TABLE 2 PE-TEOS BPSG removal Removal rate APC density removal rate rateratio (selectivity)   0 wt % 5,552 Å/min 7,596 Å/min 1.4 0.8 wt % 4,985Å/min 8,346 Å/min 1.7 2.0 wt %   949 Å/min 8,304 Å/min 8.8 2.8 wt %  168 Å/min 7,241 Å/min 43.2 4.0 wt %   135 Å/min 2,633 Å/min 19.5

As shown in Table 2 and FIG. 7, the density of APC adsorbed onto thesurface of the oxide layer increases with an increase in the density ofAPC in the slurry. Thus, adsorbed APC represses the removal of the oxidelayer during CMP and decreases the removal rate. PE-TEOS and BPSG layersperform similar to that of APC; however, the adsorbed amount of APC andthe removal rate of the PE-TEOS layer are different from the adsorbedamount of APC and the removal rate of the BPSG layer at a given densityof APC. In particular, since the BPSG layer is weaker than the oxidelayer due to the inclusion of boron and phosphorus in the BPSG layer andsince the adsorbed amount of APC in the BPSG layer is less than theadsorbed amount of APC in the oxide layer, the BPSG layer may have ahigher density of APC than the oxide layer. As a result, the removalrate ratio, e.g., the selectivity of the BPSG layer to the PE-TEOS layercan exceed 40:1 at a specific APC density.

In exemplary embodiments of the present invention, the removal rateratio of the medium material layer to the buried material layer may beover 5:1 and may be over 10:1 to reduce the occurrence of the dishingphenomenon in trench regions that have a wide width. The density of APCin the slurry may be in the range of about 2.0 to 4.5 parts by weight.

Although at least one exemplary embodiment of the present inventiondescribes the trench region 24 formed in the silicon substrate 20 asbeing filled and the surface of the trench region 24 as beingplanarized, exemplary embodiments of the present invention can beapplied to the surface planarizing process for removing steps on variousother materials, such as, for example, an insulating layer and/or aconductive layer, deposited on the silicon substrate 20.

In addition, although specific material layers such as the buried oxidelayer 28 and the medium material layer 27 have been described above,various materials which have a difference in their removal rates duringCMP can be used, and would be easily identified by one of ordinary skillin the art. Further, various types of slurries for CMP can be used toincrease the difference between the removal rates, e.g., the removalrates of the oxide layer and the BPSG layer.

According to exemplary embodiments of the present invention, a mediummaterial layer that has a higher removal rate during CMP than theremoval rate of the buried oxide layer and a CMP slurry which increasesthe removal rate ratio between the BPSG layer and the oxide layer areused. As a result, occurrences of the dishing phenomenon in thedepression region is reduced in the surface planarizing process, (e.g.,CMP, etch back, or spin-on glass), even when the width of the depressionregion (e.g., trench region) is large.

Although exemplary embodiments of this invention have been described indetail hereinabove, it should be understood by those of ordinary skillin the art that various changes in form and details may be made thereinand will still fall within the spirit and scope of the present inventionas defined in the appended claims.

1-13. (canceled)
 14. A semiconductor device comprising: a base materiallayer having a depression region; a medium material layer formed on thebottom of the depression region; and a buried material layer formed onthe medium material layer in the depression region, the buried materiallayer forming a surface co-planar with the surface of the base materiallayer.
 15. The semiconductor device of claim 14, wherein the buriedmaterial layer has a lower removal rate during chemical mechanicalpolishing than a removal rate of the medium material layer duringchemical mechanical polishing.
 16. The semiconductor device of claim 15,further comprising an etch stop layer formed on the base material layerat an outer side of the depression region.
 17. The semiconductor deviceof claim 16, wherein the buried material layer forms a surface co-planarwith the surface of the etch stop layer.
 18. The semiconductor device ofclaim 16, wherein the base material layer is a silicon substrate and thedepression region is a trench region penetrating the base materiallayer.
 19. The semiconductor device of claim 16, wherein the basematerial layer is selected from the group consisting of an insulatingmaterial layer and a conductive material layer formed on a siliconsubstrate, and the depression region is a trench region penetrating thebase material layer.
 20. The semiconductor device of claim 18, whereinthe etch stop layer is a silicon nitride layer, and the buried materiallayer is an oxide layer.
 21. The semiconductor device of claim 20,wherein the oxide layer is selected from the group consisting of aPE-TEOS layer, an HDP oxide layer and a USG layer, and the mediummaterial layer is a BPSG layer.
 22. A method for reducing the occurrenceof a dishing phenomenon in a semiconductor device comprising: forming adepression region in a base material layer; depositing a medium materiallayer on the base material layer; depositing a buried material layer;and planarizing until the medium material layer is removed and aplanarized buried material layer is formed; wherein the buried materiallayer has a lower removal rate during planarizing than a removal rate ofthe medium material layer during the planarizing.
 23. The method ofclaim 22, wherein said forming step comprises: forming an etch stoplayer pattern on the base material layer; and etching the base materiallayer using the etch stop layer pattern as an etch mask to form thedepression region.
 24. The method of claim 22, wherein said performingstep is performed until the etch stop layer pattern is exposed.
 25. Themethod of claim 22, further comprising selectively removing the mediummaterial layer from the depression region before depositing the buriedmaterial layer.
 26. The method of claim 22, wherein the planarizing stepincludes chemical mechanical polishing.
 27. The method of claim 26,wherein the base material layer is a silicon substrate, the depressionregion is a trench region penetrating the base material layer, the etchstop layer pattern is a silicon nitride layer, and the buried materiallayer is an oxide layer.
 28. The method of claim 27, wherein the oxidelayer is selected from the group consisting of a PE-TEOS layer, a USGlayer and an HDP layer.
 29. The method of claim 27, further comprisingflowing a slurry over the medium material layer and the buried materiallayer during the chemical mechanical polishing.
 30. The method of claim29, wherein the slurry contains ammonium polycarboxylate (APC) as anadditive.
 31. The method of claim 30, wherein the APC is added to theslurry in an amount of from approximately 2.0 to 4.5 parts by weight.32. The method of claim 22, further comprising forming at least one of athermal oxide layer and a silicon liner layer in the depression regionbefore depositing the buried material layer.
 33. A method of increasinga removal rate ratio of a medium material layer to a buried materiallayer comprising: adding a slurry including an anionic surfactant to acontact area on a semiconductor device; adsorbing the anionic surfactantonto the surface of at least the buried material layer; wherein theadsorbed anionic surfactant represses the removal rate of the buriedmaterial layer and increases the removal rate ratio of the mediummaterial layer to the buried material layer.
 34. The method of claim 33,wherein the buried material layer is an oxide layer selected from thegroup consisting of a PE-TEOS layer, a USG layer and an HDP layer. 35.The method of claim 34, wherein the medium material layer is a boronphosphorous silicate glass layer.
 36. The method of claim 35, whereinthe removal rate ratio is a ratio of the removal rate of the mediummaterial layer in a chemical mechanical polishing process to the removalrate of the buried material layer in a chemical mechanical polishingprocess.
 37. The method of claim 33, wherein the anionic surfactant isammonium polycarboxylate.
 38. A method of planarizing the surface of asemiconductor device, the method comprising: etching a base materiallayer having an etch stop layer pattern to form a depression region onthe base material layer; forming a medium material layer on at least theetch stop layer pattern; depositing a buried material layer on themedium material layer to fill the depression region; removing the buriedmaterial layer until the surface of the medium material layer isexposed; and planarizing the medium material layer and the buriedmaterial layer until the surface of the etch stop layer pattern isexposed to form a semiconductor device according to claim
 14. 39. Amethod for reducing the occurrence of a dishing phenomenon in asemiconductor device comprising: forming a depression region in a basematerial layer; depositing a medium material layer on the base materiallayer; depositing a buried material layer having a lower removal rateduring planarizing than a removal rate of the medium material during theplanarizing; and planarizing until the medium layer is removed and aplanarized buried material layer is formed to create a semiconductordevice according to claim 14.